It is known to mix models of hardware blocks written in the C programming language with models of hardware blocks written in the Verilog® hardware description language (HDL). These models are input to a Verilog® (hereinafter referred to as “Verilog”) simulator program, which performs the hardware simulation. One advantage of using the C programming language to construct some of the modeling blocks, rather than modeling all of the blocks in the Verilog HDL, is that it allows a higher level of abstraction to be used to create the major components of the hardware product being designed. For example, high-level C language descriptions can be written for ICs (Integrated Circuits) and modules within the ICs. These models can then be tied together early in the development cycle to form a complete system-level model. Full system level simulations can then be performed throughout the development of the product, thereby minimizing the potential for discovering system-level defects during the final integration of hardware and software.
Once the higher-level system model has been generated, each hardware block comprising the system model is then progressively refined to lower levels of abstraction by writing the lower-level model portions in the Verilog HDL until the lowest levels of the models, i.e., the gate or transistor levels, have been generated. The mixed-language capability of the simulator allows uneven, parallel development among teams designing different pieces of the project, and provides the flexibility needed to optimize full-system simulation for performance and memory usage.
One of the problems associated with existing implementations of Mixed C and Verilog simulators is the overhead involved with switching context between the Verilog and C portions of the simulation. Prior techniques have included running the C simulation as a separate process with a communication channel to the HDL simulator, or, alternatively, running the C model code and the HDL simulator in the same process, but executing the C model code directly and immediately on trigger signals when events occur in the simulator. With both techniques, a large number of context switches are required. Context switches increase processing overhead, which results in penalties in terms of simulator performance.